1. Field of the Invention
The present invention relates to the design of CMOS integrated circuits. More specifically, the present invention relates to a method and an apparatus for reducing power consumption due to gate leakage current during sleep mode in CMOS integrated circuits.
2. Related Art
Power consumption in complementary metal oxide semiconductor (CMOS) integrated circuits is made up of a dynamic term and a static term. The dynamic term arises from charging and discharging of load capacitances and is proportional to operating frequency. The static term arises from direct current (DC) flow and is independent of operating frequency. In most digital logic circuits, dynamic power is the dominant term while the chip is active. However, when the clock is stopped and the CMOS device enters a sleep mode to conserve power, static power becomes the dominant term.
The dominant components of this static power consumption are (1) subthreshold leakage currents from source to drain through transistors that are nominally OFF, and (2) gate leakage currents caused by tunneling of carriers through the very thin gate oxides. FIG. 1A illustrates subthreshold leakage current in a negative channel metal-oxide semiconductor (NMOS) transistor. This leakage current, IS, flows from the drain (d) to the source (s) when the transistor is off. FIG. 1B illustrates gate leakage current in an NMOS transistor. This current, IG, flows into the gate due to carriers tunneling across the gate oxide material. In the past, the subthreshold leakage currents have been the dominant component in the static term. However, modern circuits are being built using ever smaller gate thicknesses to improve performance. The effect of these smaller gate thicknesses is to boost the gate leakage term exponentially. FIG. 1C presents a graph illustrating the relative magnitudes of power consumption terms. As shown, dynamic power is increasing gradually with time, while the static power is increasing at a faster rate.
In many design methodologies, the same underlying design is used for system running off of alternating current (AC) or from batteries. The frequency and power supply voltage are typically reduced to cut dynamic power dissipation in battery-based systems. This will become a problem for future systems because the static power dissipation during the low-power sleep mode may unreasonably limit standby life of system such as laptop computers.
Several techniques have been suggested to minimize static power dissipation during sleep mode. Most of these techniques have sought to minimize subthreshold leakage, which has traditionally been the largest static power component. For example, higher threshold devices with less subthreshold leakage may be used, or a body bias may be applied to raise the effective threshold voltage during sleep mode. Unfortunately, these techniques do nothing to reduce gate leakage currents.
Hence, what is needed is a method and an apparatus to effectively reduce gate leakage current in CMOS integrated circuit devices during sleep mode.